Validation and Test Generation for Inductance Induced Noise on VLSI Interconnects

Advancements in integrated circuit technology have led to an increase in switching speeds of digital circuits. This increase is the primary reason why inductance induced noise (e.g., oscillation, delay, crosstalk) is beginning to cause chips to fail [3]. Thus, we now see a great interest in the inductance associated with on-chip signal lines [2]. Validation and test issues related to capacitive crosstalk noise in integrated circuits have been addressed [1]. However, test issues pertaining to inductance induced noise have not been dealt with. In this paper, we address issues pertaining to test and validation of inductance induced noise associated with interconnects. The noise generated at a noise-site may propagate to a primary output or a latch input and create logic-value errors. This motivates the validation problem. An aggressive design may not exhibit noise problems for nominal set of process parameters but may exhibit a large amount of noise in a fabricated circuit due to process variations and spot defects. This motivates the test generation problem. For our studies, we have used a 0.18 μm copper process from UMC, a fabrication facility in Taiwan. The capacitance and resistance values of the interconnects at a DC voltage are used. The self inductance of an interconnect (and the mutual inductance between interconnects) is extracted when the interconnect (or a set of interconnects) is surrounded by a ground and power mesh. It is assumed that the current returns through the entire mesh. The tool FASTHENRY is used for extracting inductance [6]. Circuit parameters and edge-rates of signals for each experiment is not discussed for reasons of space, but mentioned only when it would give an idea of the nature of circuits used for these studies.